Why does my selected signal assignment not work?
What did I do wrong with the selected signal assignment in my VHDL code?
with s select x <= a when (s = '1')
else y <= a when (s = '0');
I also tried this:
with s select x <= a when '1';
with s select y <= a when '0';
vhdl vivado
edited Nov 21 '18 at 20:53
Roman Pokrovskij
4,26294980
asked Nov 21 '18 at 15:34
Typical CowTypical Cow
11
add a comment |
What did I do wrong with the selected signal assignment in my VHDL code?
with s select x <= a when (s = '1')
else y <= a when (s = '0');
I also tried this:
with s select x <= a when '1';
with s select y <= a when '0';
vhdl vivado
edited Nov 21 '18 at 20:53
Roman Pokrovskij
4,26294980
asked Nov 21 '18 at 15:34
Typical CowTypical Cow
11
"not work" is a bit vague. Provide a Minimal, Complete, and Verifiable example including a description of the problem and the means to replicate it.
– user1155120
Nov 21 '18 at 16:23
3
Questions and answers are meant to be a search resource for future readers with questions. Without a clear problem statement (what indication do you get your signal assignment statement isn't working?) Your question isn't clear. Answering the question also likely depends on the declaration ofswhich isn't provided. A selected signal assignment has a case statement (in a process statement) equivalent. A case statement requires every choice of the value of s be covered. For type bit they are, for std_logic (std_ulogic) not. As is your question isn't answerable.
– user1155120
Nov 21 '18 at 17:01
add a comment |
What did I do wrong with the selected signal assignment in my VHDL code?
with s select x <= a when (s = '1')
else y <= a when (s = '0');
I also tried this:
with s select x <= a when '1';
with s select y <= a when '0';
vhdl vivado
edited Nov 21 '18 at 20:53
Roman Pokrovskij
4,26294980
asked Nov 21 '18 at 15:34
Typical CowTypical Cow
11
What did I do wrong with the selected signal assignment in my VHDL code?
with s select x <= a when (s = '1')
else y <= a when (s = '0');
I also tried this:
with s select x <= a when '1';
with s select y <= a when '0';
vhdl vivado
vhdl vivado
edited Nov 21 '18 at 20:53
Roman Pokrovskij
4,26294980
asked Nov 21 '18 at 15:34
Typical CowTypical Cow
11
edited Nov 21 '18 at 20:53
Roman Pokrovskij
4,26294980
asked Nov 21 '18 at 15:34
Typical CowTypical Cow
11
edited Nov 21 '18 at 20:53
Roman Pokrovskij
4,26294980
edited Nov 21 '18 at 20:53
Roman Pokrovskij
4,26294980
edited Nov 21 '18 at 20:53
Roman Pokrovskij
4,26294980
4,26294980
asked Nov 21 '18 at 15:34
Typical CowTypical Cow
11
asked Nov 21 '18 at 15:34
Typical CowTypical Cow
11
asked Nov 21 '18 at 15:34
Typical CowTypical Cow
11
11
"not work" is a bit vague. Provide a Minimal, Complete, and Verifiable example including a description of the problem and the means to replicate it.
– user1155120
Nov 21 '18 at 16:23
3
Questions and answers are meant to be a search resource for future readers with questions. Without a clear problem statement (what indication do you get your signal assignment statement isn't working?) Your question isn't clear. Answering the question also likely depends on the declaration ofswhich isn't provided. A selected signal assignment has a case statement (in a process statement) equivalent. A case statement requires every choice of the value of s be covered. For type bit they are, for std_logic (std_ulogic) not. As is your question isn't answerable.
– user1155120
Nov 21 '18 at 17:01
add a comment |
"not work" is a bit vague. Provide a Minimal, Complete, and Verifiable example including a description of the problem and the means to replicate it.
– user1155120
Nov 21 '18 at 16:23
3
Questions and answers are meant to be a search resource for future readers with questions. Without a clear problem statement (what indication do you get your signal assignment statement isn't working?) Your question isn't clear. Answering the question also likely depends on the declaration ofswhich isn't provided. A selected signal assignment has a case statement (in a process statement) equivalent. A case statement requires every choice of the value of s be covered. For type bit they are, for std_logic (std_ulogic) not. As is your question isn't answerable.
– user1155120
Nov 21 '18 at 17:01
"not work" is a bit vague. Provide a Minimal, Complete, and Verifiable example including a description of the problem and the means to replicate it.
– user1155120
Nov 21 '18 at 16:23
"not work" is a bit vague. Provide a Minimal, Complete, and Verifiable example including a description of the problem and the means to replicate it.
– user1155120
Nov 21 '18 at 16:23
3
3
Questions and answers are meant to be a search resource for future readers with questions. Without a clear problem statement (what indication do you get your signal assignment statement isn't working?) Your question isn't clear. Answering the question also likely depends on the declaration of
s which isn't provided. A selected signal assignment has a case statement (in a process statement) equivalent. A case statement requires every choice of the value of s be covered. For type bit they are, for std_logic (std_ulogic) not. As is your question isn't answerable.– user1155120
Nov 21 '18 at 17:01
Questions and answers are meant to be a search resource for future readers with questions. Without a clear problem statement (what indication do you get your signal assignment statement isn't working?) Your question isn't clear. Answering the question also likely depends on the declaration of
s which isn't provided. A selected signal assignment has a case statement (in a process statement) equivalent. A case statement requires every choice of the value of s be covered. For type bit they are, for std_logic (std_ulogic) not. As is your question isn't answerable.– user1155120
Nov 21 '18 at 17:01
add a comment |
1 Answer
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It's not completly clear what you want to do. From what you showed us, it seems to me that you want to create a demux controlled by signal s (1 input, 2 outputs), where x <= a when s='1' and y <= a when s='0'
The use of select should be done in cases when you want to create a mux (n inputs, 1 output). That is, the opposite of a demux!
I would recommend you to use a simple if statement to create a demux.
Example:
if s='1' then x <= a; else y <= a; end if;
answered Dec 19 '18 at 14:14
Nathalia DGBNathalia DGB
11
add a comment |
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1 Answer
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active
oldest
votes
1 Answer
1
active
oldest
votes
active
oldest
votes
active
oldest
votes
It's not completly clear what you want to do. From what you showed us, it seems to me that you want to create a demux controlled by signal s (1 input, 2 outputs), where x <= a when s='1' and y <= a when s='0'
The use of select should be done in cases when you want to create a mux (n inputs, 1 output). That is, the opposite of a demux!
I would recommend you to use a simple if statement to create a demux.
Example:
if s='1' then x <= a; else y <= a; end if;
answered Dec 19 '18 at 14:14
Nathalia DGBNathalia DGB
11
add a comment |
It's not completly clear what you want to do. From what you showed us, it seems to me that you want to create a demux controlled by signal s (1 input, 2 outputs), where x <= a when s='1' and y <= a when s='0'
The use of select should be done in cases when you want to create a mux (n inputs, 1 output). That is, the opposite of a demux!
I would recommend you to use a simple if statement to create a demux.
Example:
if s='1' then x <= a; else y <= a; end if;
answered Dec 19 '18 at 14:14
Nathalia DGBNathalia DGB
11
add a comment |
It's not completly clear what you want to do. From what you showed us, it seems to me that you want to create a demux controlled by signal s (1 input, 2 outputs), where x <= a when s='1' and y <= a when s='0'
The use of select should be done in cases when you want to create a mux (n inputs, 1 output). That is, the opposite of a demux!
I would recommend you to use a simple if statement to create a demux.
Example:
if s='1' then x <= a; else y <= a; end if;
answered Dec 19 '18 at 14:14
Nathalia DGBNathalia DGB
11
It's not completly clear what you want to do. From what you showed us, it seems to me that you want to create a demux controlled by signal s (1 input, 2 outputs), where x <= a when s='1' and y <= a when s='0'
The use of select should be done in cases when you want to create a mux (n inputs, 1 output). That is, the opposite of a demux!
I would recommend you to use a simple if statement to create a demux.
Example:
if s='1' then x <= a; else y <= a; end if;
answered Dec 19 '18 at 14:14
Nathalia DGBNathalia DGB
11
answered Dec 19 '18 at 14:14
Nathalia DGBNathalia DGB
11
answered Dec 19 '18 at 14:14
Nathalia DGBNathalia DGB
11
answered Dec 19 '18 at 14:14
Nathalia DGBNathalia DGB
11
11
add a comment |
add a comment |
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"not work" is a bit vague. Provide a Minimal, Complete, and Verifiable example including a description of the problem and the means to replicate it.
– user1155120
Nov 21 '18 at 16:23
3
Questions and answers are meant to be a search resource for future readers with questions. Without a clear problem statement (what indication do you get your signal assignment statement isn't working?) Your question isn't clear. Answering the question also likely depends on the declaration of
swhich isn't provided. A selected signal assignment has a case statement (in a process statement) equivalent. A case statement requires every choice of the value of s be covered. For type bit they are, for std_logic (std_ulogic) not. As is your question isn't answerable.– user1155120
Nov 21 '18 at 17:01