No Q bar on flip-flop
$begingroup$
I'm currently using Quartus and I'm trying to make a 4 bit counter. I noticed that when I imported the built-in flip-flop that there is no Q bar output. It's the same issue with the JK flip-flop as well. I'm trying to make an asynchronous up counter
I need the Q Bar output as this will be connected to the 'D' input. I was thinking about adding the inverter on the Q output but I can't, as I'm making an up counter.
Thanks to all in advance.
fpga flipflop
edited Nov 25 '18 at 18:45
SamGibson
11.5k41738
asked Nov 25 '18 at 17:59
NeamusNeamus
1358
$endgroup$
add a comment |
$begingroup$
I'm currently using Quartus and I'm trying to make a 4 bit counter. I noticed that when I imported the built-in flip-flop that there is no Q bar output. It's the same issue with the JK flip-flop as well. I'm trying to make an asynchronous up counter
I need the Q Bar output as this will be connected to the 'D' input. I was thinking about adding the inverter on the Q output but I can't, as I'm making an up counter.
Thanks to all in advance.
fpga flipflop
edited Nov 25 '18 at 18:45
SamGibson
11.5k41738
asked Nov 25 '18 at 17:59
NeamusNeamus
1358
$endgroup$
6
$begingroup$
The question makes no sense. Why would anything prevent you from creating "Q-bar" using an inverter? You can still use "Q"...
$endgroup$
– Dave Tweed♦
Nov 25 '18 at 18:05
$begingroup$
Q is meant to be the output and the Q' was meant to connect to the clock aswell as the 'D' input
$endgroup$
– Neamus
Nov 25 '18 at 18:11
6
$begingroup$
@Neamus But that's not an answer. Q-bar is the inverse of Q. By definition, that's what it is - that's what the bar means. So if you don't have a Q-bar provided, invert Q and you have a Q-bar signal.
$endgroup$
– Graham
Nov 25 '18 at 20:12
add a comment |
$begingroup$
I'm currently using Quartus and I'm trying to make a 4 bit counter. I noticed that when I imported the built-in flip-flop that there is no Q bar output. It's the same issue with the JK flip-flop as well. I'm trying to make an asynchronous up counter
I need the Q Bar output as this will be connected to the 'D' input. I was thinking about adding the inverter on the Q output but I can't, as I'm making an up counter.
Thanks to all in advance.
fpga flipflop
edited Nov 25 '18 at 18:45
SamGibson
11.5k41738
asked Nov 25 '18 at 17:59
NeamusNeamus
1358
$endgroup$
I'm currently using Quartus and I'm trying to make a 4 bit counter. I noticed that when I imported the built-in flip-flop that there is no Q bar output. It's the same issue with the JK flip-flop as well. I'm trying to make an asynchronous up counter
I need the Q Bar output as this will be connected to the 'D' input. I was thinking about adding the inverter on the Q output but I can't, as I'm making an up counter.
Thanks to all in advance.
fpga flipflop
fpga flipflop
edited Nov 25 '18 at 18:45
SamGibson
11.5k41738
asked Nov 25 '18 at 17:59
NeamusNeamus
1358
edited Nov 25 '18 at 18:45
SamGibson
11.5k41738
asked Nov 25 '18 at 17:59
NeamusNeamus
1358
edited Nov 25 '18 at 18:45
SamGibson
11.5k41738
edited Nov 25 '18 at 18:45
SamGibson
11.5k41738
edited Nov 25 '18 at 18:45
SamGibson
11.5k41738
11.5k41738
asked Nov 25 '18 at 17:59
NeamusNeamus
1358
asked Nov 25 '18 at 17:59
NeamusNeamus
1358
asked Nov 25 '18 at 17:59
NeamusNeamus
1358
1358
6
$begingroup$
The question makes no sense. Why would anything prevent you from creating "Q-bar" using an inverter? You can still use "Q"...
$endgroup$
– Dave Tweed♦
Nov 25 '18 at 18:05
$begingroup$
Q is meant to be the output and the Q' was meant to connect to the clock aswell as the 'D' input
$endgroup$
– Neamus
Nov 25 '18 at 18:11
6
$begingroup$
@Neamus But that's not an answer. Q-bar is the inverse of Q. By definition, that's what it is - that's what the bar means. So if you don't have a Q-bar provided, invert Q and you have a Q-bar signal.
$endgroup$
– Graham
Nov 25 '18 at 20:12
add a comment |
6
$begingroup$
The question makes no sense. Why would anything prevent you from creating "Q-bar" using an inverter? You can still use "Q"...
$endgroup$
– Dave Tweed♦
Nov 25 '18 at 18:05
$begingroup$
Q is meant to be the output and the Q' was meant to connect to the clock aswell as the 'D' input
$endgroup$
– Neamus
Nov 25 '18 at 18:11
6
$begingroup$
@Neamus But that's not an answer. Q-bar is the inverse of Q. By definition, that's what it is - that's what the bar means. So if you don't have a Q-bar provided, invert Q and you have a Q-bar signal.
$endgroup$
– Graham
Nov 25 '18 at 20:12
6
6
$begingroup$
The question makes no sense. Why would anything prevent you from creating "Q-bar" using an inverter? You can still use "Q"...
$endgroup$
– Dave Tweed♦
Nov 25 '18 at 18:05
$begingroup$
The question makes no sense. Why would anything prevent you from creating "Q-bar" using an inverter? You can still use "Q"...
$endgroup$
– Dave Tweed♦
Nov 25 '18 at 18:05
$begingroup$
Q is meant to be the output and the Q' was meant to connect to the clock aswell as the 'D' input
$endgroup$
– Neamus
Nov 25 '18 at 18:11
$begingroup$
Q is meant to be the output and the Q' was meant to connect to the clock aswell as the 'D' input
$endgroup$
– Neamus
Nov 25 '18 at 18:11
6
6
$begingroup$
@Neamus But that's not an answer. Q-bar is the inverse of Q. By definition, that's what it is - that's what the bar means. So if you don't have a Q-bar provided, invert Q and you have a Q-bar signal.
$endgroup$
– Graham
Nov 25 '18 at 20:12
$begingroup$
@Neamus But that's not an answer. Q-bar is the inverse of Q. By definition, that's what it is - that's what the bar means. So if you don't have a Q-bar provided, invert Q and you have a Q-bar signal.
$endgroup$
– Graham
Nov 25 '18 at 20:12
add a comment |
2 Answers
2
active
oldest
votes
$begingroup$
FFs on FPGAs don't have explicit "Q-bar" outputs, because inverters are basically available "for free" as a result of how logic is implemented in LUTs (lookup tables).
You can just add the inverter, and it will be incorporated into every LUT that it feeds.
In any case, a ripple counter like the one you have shown is a poor choice for FPGA implementation. It is far better to use a synchronous counter.
answered Nov 25 '18 at 18:07
Dave Tweed♦Dave Tweed
121k9151259
$endgroup$
5
$begingroup$
I would be rather surprised if Quartus will let you build a ripple counter without bitching, most FPGA tools do not like mixing clock and data because it makes timing closure hard. If you just write a register with a input <= output + 1 wrapped around it the tool will probably use one of the built in carry chains to build your counter for you (and it will be properly synchronous).
$endgroup$
– Dan Mills
Nov 25 '18 at 18:55
$begingroup$
Oooh, “Q-bar” means “Q'” i.e. the inverse, “NOT Q”?. Never heard that term before.
$endgroup$
– Michael
Nov 25 '18 at 21:06
$begingroup$
@DanMills Depends on the FPGA, I guess, there are a few Intel FPGA's that have surprisingly finely meshed clock nets and these might be able to do it. But in general, yeah, there's no reason for this bit fiddling anymore. Most of these questions either complete beginner hobby projects or some inane uni task.
$endgroup$
– DonFusili
Nov 26 '18 at 8:55
add a comment |
$begingroup$
You can add an inverter, and then you'll add some combinatorial logic on each D input to get a synchronous up counter. Or you could make a ring counter.
answered Nov 25 '18 at 18:06
Spehro PefhanySpehro Pefhany
210k5162425
$endgroup$
add a comment |
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2 Answers
2
active
oldest
votes
2 Answers
2
active
oldest
votes
active
oldest
votes
active
oldest
votes
$begingroup$
FFs on FPGAs don't have explicit "Q-bar" outputs, because inverters are basically available "for free" as a result of how logic is implemented in LUTs (lookup tables).
You can just add the inverter, and it will be incorporated into every LUT that it feeds.
In any case, a ripple counter like the one you have shown is a poor choice for FPGA implementation. It is far better to use a synchronous counter.
answered Nov 25 '18 at 18:07
Dave Tweed♦Dave Tweed
121k9151259
$endgroup$
5
$begingroup$
I would be rather surprised if Quartus will let you build a ripple counter without bitching, most FPGA tools do not like mixing clock and data because it makes timing closure hard. If you just write a register with a input <= output + 1 wrapped around it the tool will probably use one of the built in carry chains to build your counter for you (and it will be properly synchronous).
$endgroup$
– Dan Mills
Nov 25 '18 at 18:55
$begingroup$
Oooh, “Q-bar” means “Q'” i.e. the inverse, “NOT Q”?. Never heard that term before.
$endgroup$
– Michael
Nov 25 '18 at 21:06
$begingroup$
@DanMills Depends on the FPGA, I guess, there are a few Intel FPGA's that have surprisingly finely meshed clock nets and these might be able to do it. But in general, yeah, there's no reason for this bit fiddling anymore. Most of these questions either complete beginner hobby projects or some inane uni task.
$endgroup$
– DonFusili
Nov 26 '18 at 8:55
add a comment |
$begingroup$
FFs on FPGAs don't have explicit "Q-bar" outputs, because inverters are basically available "for free" as a result of how logic is implemented in LUTs (lookup tables).
You can just add the inverter, and it will be incorporated into every LUT that it feeds.
In any case, a ripple counter like the one you have shown is a poor choice for FPGA implementation. It is far better to use a synchronous counter.
answered Nov 25 '18 at 18:07
Dave Tweed♦Dave Tweed
121k9151259
$endgroup$
5
$begingroup$
I would be rather surprised if Quartus will let you build a ripple counter without bitching, most FPGA tools do not like mixing clock and data because it makes timing closure hard. If you just write a register with a input <= output + 1 wrapped around it the tool will probably use one of the built in carry chains to build your counter for you (and it will be properly synchronous).
$endgroup$
– Dan Mills
Nov 25 '18 at 18:55
$begingroup$
Oooh, “Q-bar” means “Q'” i.e. the inverse, “NOT Q”?. Never heard that term before.
$endgroup$
– Michael
Nov 25 '18 at 21:06
$begingroup$
@DanMills Depends on the FPGA, I guess, there are a few Intel FPGA's that have surprisingly finely meshed clock nets and these might be able to do it. But in general, yeah, there's no reason for this bit fiddling anymore. Most of these questions either complete beginner hobby projects or some inane uni task.
$endgroup$
– DonFusili
Nov 26 '18 at 8:55
add a comment |
$begingroup$
FFs on FPGAs don't have explicit "Q-bar" outputs, because inverters are basically available "for free" as a result of how logic is implemented in LUTs (lookup tables).
You can just add the inverter, and it will be incorporated into every LUT that it feeds.
In any case, a ripple counter like the one you have shown is a poor choice for FPGA implementation. It is far better to use a synchronous counter.
answered Nov 25 '18 at 18:07
Dave Tweed♦Dave Tweed
121k9151259
$endgroup$
FFs on FPGAs don't have explicit "Q-bar" outputs, because inverters are basically available "for free" as a result of how logic is implemented in LUTs (lookup tables).
You can just add the inverter, and it will be incorporated into every LUT that it feeds.
In any case, a ripple counter like the one you have shown is a poor choice for FPGA implementation. It is far better to use a synchronous counter.
answered Nov 25 '18 at 18:07
Dave Tweed♦Dave Tweed
121k9151259
answered Nov 25 '18 at 18:07
Dave Tweed♦Dave Tweed
121k9151259
answered Nov 25 '18 at 18:07
Dave Tweed♦Dave Tweed
121k9151259
answered Nov 25 '18 at 18:07
Dave Tweed♦Dave Tweed
121k9151259
121k9151259
5
$begingroup$
I would be rather surprised if Quartus will let you build a ripple counter without bitching, most FPGA tools do not like mixing clock and data because it makes timing closure hard. If you just write a register with a input <= output + 1 wrapped around it the tool will probably use one of the built in carry chains to build your counter for you (and it will be properly synchronous).
$endgroup$
– Dan Mills
Nov 25 '18 at 18:55
$begingroup$
Oooh, “Q-bar” means “Q'” i.e. the inverse, “NOT Q”?. Never heard that term before.
$endgroup$
– Michael
Nov 25 '18 at 21:06
$begingroup$
@DanMills Depends on the FPGA, I guess, there are a few Intel FPGA's that have surprisingly finely meshed clock nets and these might be able to do it. But in general, yeah, there's no reason for this bit fiddling anymore. Most of these questions either complete beginner hobby projects or some inane uni task.
$endgroup$
– DonFusili
Nov 26 '18 at 8:55
add a comment |
5
$begingroup$
I would be rather surprised if Quartus will let you build a ripple counter without bitching, most FPGA tools do not like mixing clock and data because it makes timing closure hard. If you just write a register with a input <= output + 1 wrapped around it the tool will probably use one of the built in carry chains to build your counter for you (and it will be properly synchronous).
$endgroup$
– Dan Mills
Nov 25 '18 at 18:55
$begingroup$
Oooh, “Q-bar” means “Q'” i.e. the inverse, “NOT Q”?. Never heard that term before.
$endgroup$
– Michael
Nov 25 '18 at 21:06
$begingroup$
@DanMills Depends on the FPGA, I guess, there are a few Intel FPGA's that have surprisingly finely meshed clock nets and these might be able to do it. But in general, yeah, there's no reason for this bit fiddling anymore. Most of these questions either complete beginner hobby projects or some inane uni task.
$endgroup$
– DonFusili
Nov 26 '18 at 8:55
5
5
$begingroup$
I would be rather surprised if Quartus will let you build a ripple counter without bitching, most FPGA tools do not like mixing clock and data because it makes timing closure hard. If you just write a register with a input <= output + 1 wrapped around it the tool will probably use one of the built in carry chains to build your counter for you (and it will be properly synchronous).
$endgroup$
– Dan Mills
Nov 25 '18 at 18:55
$begingroup$
I would be rather surprised if Quartus will let you build a ripple counter without bitching, most FPGA tools do not like mixing clock and data because it makes timing closure hard. If you just write a register with a input <= output + 1 wrapped around it the tool will probably use one of the built in carry chains to build your counter for you (and it will be properly synchronous).
$endgroup$
– Dan Mills
Nov 25 '18 at 18:55
$begingroup$
Oooh, “Q-bar” means “Q'” i.e. the inverse, “NOT Q”?. Never heard that term before.
$endgroup$
– Michael
Nov 25 '18 at 21:06
$begingroup$
Oooh, “Q-bar” means “Q'” i.e. the inverse, “NOT Q”?. Never heard that term before.
$endgroup$
– Michael
Nov 25 '18 at 21:06
$begingroup$
@DanMills Depends on the FPGA, I guess, there are a few Intel FPGA's that have surprisingly finely meshed clock nets and these might be able to do it. But in general, yeah, there's no reason for this bit fiddling anymore. Most of these questions either complete beginner hobby projects or some inane uni task.
$endgroup$
– DonFusili
Nov 26 '18 at 8:55
$begingroup$
@DanMills Depends on the FPGA, I guess, there are a few Intel FPGA's that have surprisingly finely meshed clock nets and these might be able to do it. But in general, yeah, there's no reason for this bit fiddling anymore. Most of these questions either complete beginner hobby projects or some inane uni task.
$endgroup$
– DonFusili
Nov 26 '18 at 8:55
add a comment |
$begingroup$
You can add an inverter, and then you'll add some combinatorial logic on each D input to get a synchronous up counter. Or you could make a ring counter.
answered Nov 25 '18 at 18:06
Spehro PefhanySpehro Pefhany
210k5162425
$endgroup$
add a comment |
$begingroup$
You can add an inverter, and then you'll add some combinatorial logic on each D input to get a synchronous up counter. Or you could make a ring counter.
answered Nov 25 '18 at 18:06
Spehro PefhanySpehro Pefhany
210k5162425
$endgroup$
add a comment |
$begingroup$
You can add an inverter, and then you'll add some combinatorial logic on each D input to get a synchronous up counter. Or you could make a ring counter.
answered Nov 25 '18 at 18:06
Spehro PefhanySpehro Pefhany
210k5162425
$endgroup$
You can add an inverter, and then you'll add some combinatorial logic on each D input to get a synchronous up counter. Or you could make a ring counter.
answered Nov 25 '18 at 18:06
Spehro PefhanySpehro Pefhany
210k5162425
answered Nov 25 '18 at 18:06
Spehro PefhanySpehro Pefhany
210k5162425
answered Nov 25 '18 at 18:06
Spehro PefhanySpehro Pefhany
210k5162425
answered Nov 25 '18 at 18:06
Spehro PefhanySpehro Pefhany
210k5162425
210k5162425
add a comment |
add a comment |
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$begingroup$
The question makes no sense. Why would anything prevent you from creating "Q-bar" using an inverter? You can still use "Q"...
$endgroup$
– Dave Tweed♦
Nov 25 '18 at 18:05
$begingroup$
Q is meant to be the output and the Q' was meant to connect to the clock aswell as the 'D' input
$endgroup$
– Neamus
Nov 25 '18 at 18:11
6
$begingroup$
@Neamus But that's not an answer. Q-bar is the inverse of Q. By definition, that's what it is - that's what the bar means. So if you don't have a Q-bar provided, invert Q and you have a Q-bar signal.
$endgroup$
– Graham
Nov 25 '18 at 20:12