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A schematic by Lattice Semiconductor includes the diagrammed D flip-flop. This D flip/flop accepts, among others, a Set/Reset signal.

I would have understood a Set signal. I would have understood a Reset signal. I would even have understood Set and Reset signals on separate lines. I cannot, however, understand a joint Set/Reset signal.

  -------------------

  |                 |

--| D             Q |--

--| CLOCK ENABLE    |

--|>CLOCK           |

  |                 |

  |    SET/RESET    |

  ------------------

           |

QUESTION

What is a Set/Reset signal, please?

ADDITIONAL INFORMATION

For optional reference, here is the data sheet (1.5 MB) in which the D flip-flop appears, in Figure 3.2, page 9. I do not, of course, ask you to go to read a 52-page data sheet for me! (That would be my homework, not yours.) Therefore, the relevant quotes from the data sheet as far as I know are as follows.

Each logic cell includes ... a D-style flip-flop (DFF), with an optional clock-enable and reset control input.... [Sect. 3.1.1, page 9.]

... Signal description [is as follows].

• Function: input.


• Type: control signal.


• Signal name: Set/Reset. (Footnote: if Set/Reset is not used, then the flip-flop is never set/reset, except when cleared immediately after configuration).


• Description: Asynchronous or synchronous local set/reset shared by [a block of eight logic cells, each cell including a flip-flop]. [Table 3.1, page 10.]

One can externally disable the Set/Reset signal, presumably via multiplexing or high-Z pull-down, but I see nothing to decide whether the Set/Reset signal—when not disabled—should set the flip-flop or reset it.

Am I missing something?

If you know what a Set/Reset signal is, would you tell me?

In all likelihood it isn't really a "set/reset" signal, so much as a signal that can be configured to be either set or reset depending on how the device is configured. Note that in figure 3.2 (copied below for clarity), it says "flip-flop with optional [...] set or reset controls".

Similarly it will also be the configuration bits that disable the signal entirely if unused. You can see this in figure 3.2:

D types combine the set and reset pins with an inverter so that the set and reset pins are in opposite states, that prevents the forbidden state of neither set.

Source: Electronic Tutorials - The D-type Flip Flop

"The D-type flip-flop is a modified Set-Reset flip-flop with the addition of an inverter to prevent the S and R inputs from being at the same logic level.

One of the main disadvantages of the basic SR NAND Gate Bistable circuit is that the indeterminate input condition of SET = “0” and RESET = “0” is forbidden.

This state will force both outputs to be at logic “1”, over-riding the feedback latching action and whichever input goes to logic level “1” first will lose control, while the other input still at logic “0” controls the resulting state of the latch.

But in order to prevent this from happening an inverter can be connected between the “SET” and the “RESET” inputs to produce another type of flip flop circuit known as a Data Latch, Delay flip flop, D-type Bistable, D-type Flip Flop or just simply a D Flip Flop as it is more generally called.".

Source: Hyperphysics - Clocked D Flip-Flop

"The D flip-flop tries to follow the input D but cannot make the required transitions unless it is enabled by the clock. Note that if the clock is low when a transition in D occurs, the tracking transiton in Q occurs at the next upward transition of the clock.".

If the DFF block were instead a D FF made from NAND latches it would look like this: