Verilog case ignoring conditional
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EDIT: I seemed to have gotten the original program working by always adding an else after an if statement, and not putting 'Y = Y' for example. So in this case would be B: Y = B instead.
I'm unsure the reason its working now though, seems like something I don't have the correct experience to understand.
I am trying to emulate a state machine in verilog, but I am having problems understanding a specific problem. The original code was much larger, but I cut it down to what is producing an effect I cannot explain. (Not an actual implementation, just example showing my problem)
I have 'Y' store the "state" im in, and will have it change depending on its state, and conditionals. My problem is that the line for case A:, ignore the conditional and makes Y = B, even though enter is always low. I have 'ts' output whether it is in fact in the state B.
If i replace 'enter == 1' with '0 == 1', i get the same output.
module ComboCheckF(Clock,enter,ts);
input Clock, enter;
output ts;
reg[3:0] Y;
parameter A = 4'b0000, B = 4'b0001;
initial Y = A;
always @(enter,Y)
begin
case(Y)
A: if (enter == 1) Y = B;
else Y = Y;
B: Y = Y;
default: Y = 4'bxxxx;
endcase
end
assign ts=(Y==B);
endmodule
and the output (can ignore clock, was leftover)
verilog intel state-machines
asked Nov 20 at 4:30
user2958503
515
add a comment |
up vote
0
down vote
favorite
EDIT: I seemed to have gotten the original program working by always adding an else after an if statement, and not putting 'Y = Y' for example. So in this case would be B: Y = B instead.
I'm unsure the reason its working now though, seems like something I don't have the correct experience to understand.
I am trying to emulate a state machine in verilog, but I am having problems understanding a specific problem. The original code was much larger, but I cut it down to what is producing an effect I cannot explain. (Not an actual implementation, just example showing my problem)
I have 'Y' store the "state" im in, and will have it change depending on its state, and conditionals. My problem is that the line for case A:, ignore the conditional and makes Y = B, even though enter is always low. I have 'ts' output whether it is in fact in the state B.
If i replace 'enter == 1' with '0 == 1', i get the same output.
module ComboCheckF(Clock,enter,ts);
input Clock, enter;
output ts;
reg[3:0] Y;
parameter A = 4'b0000, B = 4'b0001;
initial Y = A;
always @(enter,Y)
begin
case(Y)
A: if (enter == 1) Y = B;
else Y = Y;
B: Y = Y;
default: Y = 4'bxxxx;
endcase
end
assign ts=(Y==B);
endmodule
and the output (can ignore clock, was leftover)
verilog intel state-machines
asked Nov 20 at 4:30
user2958503
515
2
Bis missing form your sensitivity list. To prevent errors like this usealways @( * )
– Oldfart
Nov 20 at 8:14
add a comment |
up vote
0
down vote
favorite
up vote
0
down vote
favorite
EDIT: I seemed to have gotten the original program working by always adding an else after an if statement, and not putting 'Y = Y' for example. So in this case would be B: Y = B instead.
I'm unsure the reason its working now though, seems like something I don't have the correct experience to understand.
I am trying to emulate a state machine in verilog, but I am having problems understanding a specific problem. The original code was much larger, but I cut it down to what is producing an effect I cannot explain. (Not an actual implementation, just example showing my problem)
I have 'Y' store the "state" im in, and will have it change depending on its state, and conditionals. My problem is that the line for case A:, ignore the conditional and makes Y = B, even though enter is always low. I have 'ts' output whether it is in fact in the state B.
If i replace 'enter == 1' with '0 == 1', i get the same output.
module ComboCheckF(Clock,enter,ts);
input Clock, enter;
output ts;
reg[3:0] Y;
parameter A = 4'b0000, B = 4'b0001;
initial Y = A;
always @(enter,Y)
begin
case(Y)
A: if (enter == 1) Y = B;
else Y = Y;
B: Y = Y;
default: Y = 4'bxxxx;
endcase
end
assign ts=(Y==B);
endmodule
and the output (can ignore clock, was leftover)
verilog intel state-machines
asked Nov 20 at 4:30
user2958503
515
EDIT: I seemed to have gotten the original program working by always adding an else after an if statement, and not putting 'Y = Y' for example. So in this case would be B: Y = B instead.
I'm unsure the reason its working now though, seems like something I don't have the correct experience to understand.
I am trying to emulate a state machine in verilog, but I am having problems understanding a specific problem. The original code was much larger, but I cut it down to what is producing an effect I cannot explain. (Not an actual implementation, just example showing my problem)
I have 'Y' store the "state" im in, and will have it change depending on its state, and conditionals. My problem is that the line for case A:, ignore the conditional and makes Y = B, even though enter is always low. I have 'ts' output whether it is in fact in the state B.
If i replace 'enter == 1' with '0 == 1', i get the same output.
module ComboCheckF(Clock,enter,ts);
input Clock, enter;
output ts;
reg[3:0] Y;
parameter A = 4'b0000, B = 4'b0001;
initial Y = A;
always @(enter,Y)
begin
case(Y)
A: if (enter == 1) Y = B;
else Y = Y;
B: Y = Y;
default: Y = 4'bxxxx;
endcase
end
assign ts=(Y==B);
endmodule
and the output (can ignore clock, was leftover)
verilog intel state-machines
verilog intel state-machines
asked Nov 20 at 4:30
user2958503
515
asked Nov 20 at 4:30
user2958503
515
edited Nov 20 at 5:44
asked Nov 20 at 4:30
user2958503
515
asked Nov 20 at 4:30
user2958503
515
asked Nov 20 at 4:30
user2958503
515
515
2
Bis missing form your sensitivity list. To prevent errors like this usealways @( * )
– Oldfart
Nov 20 at 8:14
add a comment |
2
Bis missing form your sensitivity list. To prevent errors like this usealways @( * )
– Oldfart
Nov 20 at 8:14
2
2
B is missing form your sensitivity list. To prevent errors like this use always @( * ) – Oldfart
Nov 20 at 8:14
B is missing form your sensitivity list. To prevent errors like this use always @( * ) – Oldfart
Nov 20 at 8:14
add a comment |
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Bis missing form your sensitivity list. To prevent errors like this usealways @( * )– Oldfart
Nov 20 at 8:14